LSI Logic Unveils Industry's Highest Speed DDR-2 SDRAM Physical Layer Memory Interface
- High speed DDR-2 interface core and I/O provide customers a physical layer solution that is easily integrated into their ASIC
- Cuts time, cost and complexity of OEM product development
- Capability enables customers to develop next generation platforms using high performance, high density DDR-2 SDRAMs
MILPITAS, Calif. - June 1, 2004 - LSI Logic Corporation (NYSE: LSI) today introduced a physical layer memory interface that can save customers months of development time while improving product performance with the industrys highest speed DDR-2 SDRAM technology. LSI Logics new DDR-2 ASIC core is the first physical layer interface and I/O buffer to support 333MHz/667Mbps data speeds, enabling manufacturers of data storage, communications, multi-function printers, industrial and medical equipment to take advantage of the memory technologys superior density, bandwidth and lower cost.
LSI Logics DDR-2 core with SSTL18 I/O interface buffer can be quickly and easily integrated with a customers own logic for fast system-on-a-chip (SoC) designs. The DDR-2 is a pre-verified interface validated in silicon, significantly reducing the turnaround time and risk of chip development.
LSI Logic has been highly successful with two generations of memory interface cores, said Jean Bou-Farhat, vice president, CoreWare® Division, LSI Logic Corporation. The DDR-2 cores allow our customers to take advantage of the performance and cost benefits offered by DDR-2 SDRAM memory products. This new addition to the CoreWare library, combined with existing connectivity solutions, helps our customers design systems efficiently and quickly while also reducing risk.
LSI Logics DDR-2 physical layer interface with pre-verified functionality, layout and timing closure combined with silicon validation, significantly reduces the risk and turnaround time of chip development. The SSTL18 I/O buffer, with features including On-Die Termination (ODT), impedance controlled driver, and precision duty cycle matching, provide an electrical interface of superior signal integrity ensuring optimal performance and first pass success. The DDR-2 cores and SSTL18 I/O are immediately available for customer design-ins and are easy to integrate into an ASIC design.
